Tim 'mithro' Ansell

Only Al bonds at the moment. @stuart is your person for custom wire bonding contracts.

We've now got a partner who can do gold wire bonding - not the stud bumping though.

1

Does someone know if we can have core_VDD > IO_VDD when using the ocd IO? (edited)

Aside from the totally fair objection of "wtf are you doing?" is there anything that would technically prevent me from doing this, such as a diode between core_vdd and io_vdd?

No you can't

5:15 p.m.

(1) There is a parasitic body diode. (2) level converters are not the same to up convert or down convert ... so that wouldn't work anyway.

1

tnt

(1) There is a parasitic body diode. (2) level converters are not the same to up convert or down convert ... so that wouldn't work anyway.

Thanks tnt

(edited)

I was reading the PDK documentation for our IO cells a few days ago, and they mention we don't have circuit under the pad on the IO cells in order to comply with the restrictions of the 3 metal layer process (gf180mcuA). So since we are targeting mcuD does this mean there is an opportunity to shorten the io pads by as much as 75um if they where reworked ?

The bond pad is non-CUP due to design manual restriction on 3LM.

(edited)

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Given the trouble with bonding I'm not sure I would go to CUP ...

Tim Edwards

See https://github.com/fossi-foundation/frigate_analog. Basically a field-programmable analog array with DACs, ADCs, instrumentation amplifiers, temperature sensor, etc., etc. Hard to port from sky130 to another process, but I would like to do that for GF180MCU and IHP sg13g2 eventually.

Did this get ported to GF180?

@Archit3ch (George) : No, that did not get ported to GF180. The Chipalooza challenge is a step in that direction.

Essen started a thread. 2026-09-04 2:30 p.m.

namibj

You don't happen to have the skills it takes to figure decently efficient hyperparameters for letting Xyce simulate up to a couple mm^2 of gf180mcuD PEX extraction, or do you? I lack the background to know how to tune the bunch of solver options and solver choices offered

I'm just seeing it being highly stalling on memory with also sadly substantial lacks in reasonable prefetching behavior (it's nowhere near 30% bandwidth utilization and hovers around 0.02~0.05 IPC... Yeah it's bad.)

I have a few ideas... Not at that scale and not with real Xyce models though.

Archit3ch (George)

I have a few ideas... Not at that scale and not with real Xyce models though.

Great. Let's chat later starting in like 2 hours from now, or up to a couple hours later than that?

Essen

I was reading the PDK documentation for our IO cells a few days ago, and they mention we don't have circuit under the pad on the IO cells in order to comply with the restrictions of the 3 metal layer process (gf180mcuA). So since we are targeting mcuD does this mean there is an opportunity to shorten the io pads by as much as 75um if they where reworked ?

The bond pad is non-CUP due to design manual restriction on 3LM.

(edited)

CUP isn't allowed for wedge bonds iirc even at more layers.

namibj

Great. Let's chat later starting in like 2 hours from now, or up to a couple hours later than that?

I'm travelling without a laptop. Currently on the metro. I can share a 1000-foot plan.

@Tholin Check out your WSLG design in high resolution: https://infosec.exchange/@infosecdj/117213266219165204 Dmitry is working through the dies I sent him, more to follow soon

DJ🌞:donor: (@infosecdj@infosec.exchange)

Hello #NakedDieFriday fans, hope you did not miss me too much. Here is this week's eye candy for you. Supplied by good folks at wafer.space/ was a batch of die samples from their first production run. Here is one of them -- a die-sized doodle of their logo. It is open source too: github.com/89Mods/ws-logo-die There is circuitry there apart from the logo, but the project readme does not say what it does. :-) Full-res map: infosecdj.net/map/wafer-space/…

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Archit3ch (George)

I'm travelling without a laptop. Currently on the metro. I can share a 1000-foot plan.

I was thinking maybe a discord voice call whenever convenient for you within the approximate time frame I mentioned?

3:59 p.m.

Add me (discord friend; but let me know so here if you do) if you want btw. (edited)

namibj

CUP isn't allowed for wedge bonds iirc even at more layers.

https://discord.com/channels/1361349522684510449/1545289242417307678/1545442323041886250

Leo Moser (mole99)

@Tholin Check out your WSLG design in high resolution: https://infosec.exchange/@infosecdj/117213266219165204 Dmitry is working through the dies I sent him, more to follow soon

yeah more of that is coming -- let me know if you want them posted here :)

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InfoSecDJ

yeah more of that is coming -- let me know if you want them posted here :)

Feel free to post the ones you've already imaged, if you like

Once you've finished the whole batch, we can make an announcement for all to see.

@Leo Moser (mole99) http://infosecdj.net:8086/map/#wafer-space

12:08 p.m.

No TT ones

tnt

No TT ones

Yes, it seems that the package prepared by Tim didn't include any of the TTP2/TTPG dies. If you still have any left over, maybe you could get those to Dmitry?

Leo Moser (mole99)

Yes, it seems that the package prepared by Tim didn't include any of the TTP2/TTPG dies. If you still have any left over, maybe you could get those to Dmitry?

I have some from Tim which I did not get to yet, maybe these are the ones?

1

I guess we'll find out

1

some more eye candy for you folks

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2:35 p.m.

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-mosb/infosecdj_mz_nikpa40x

2:36 p.m.

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-ishi/infosecdj_mz_nikpa40x

2:36 p.m.

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-as03/infosecdj_mz_nikpa40x

InfoSecDJ

I have some from Tim which I did not get to yet, maybe these are the ones?

Honestly, I'd expect a spare raw ttgf0p2 die for such imaging to be easily furnished and it's not like that'd be hard to send to you.

namibj

Honestly, I'd expect a spare raw ttgf0p2 die for such imaging to be easily furnished and it's not like that'd be hard to send to you.

Good to know. Let's get back to it after I am through all the samples on hand.

Thinking of designing the PCBs to bring-up my run 2 chips already

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Do we know yet what the COB PCB layout will be for run 2?

https://github.com/jonahsaunders/inductor-studio/tree/main

GitHub - jonahsaunders/inductor-studio

Contribute to jonahsaunders/inductor-studio development by creating an account on GitHub.

9:56 p.m.

I made this with the new GPT-6 Astra in 20 minutes Haven't tested it thoroughly, but just did it as a test

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Tholin

Do we know yet what the COB PCB layout will be for run 2?

I’m gonna assume the default COB PCB is the same as last time. I did not customize the padring this time.

Tholin

I’m gonna assume the default COB PCB is the same as last time. I did not customize the padring this time.

I’m fairly certain pinout won’t change for 1x1. Finer details like number of layers and position of vias might. Pinout for 1x0p5 might change slightly as the ordering of 4 pins is reversed compared to the die which is likely a recipe for confusion in future I don’t think 0p5x1 would change, but the run 1 ones aren’t tested yet. For quarter slot there was talk of using a different connector (fewer pins = cheaper)

Leo Moser (mole99)

Yes, it seems that the package prepared by Tim didn't include any of the TTP2/TTPG dies. If you still have any left over, maybe you could get those to Dmitry?

I have no idea what the package was that I gave you

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InfoSecDJ

some more eye candy for you folks

These are super cool!

InfoSecDJ

some more eye candy for you folks

I would love to host a copy on https://data.wafer.space

9:22 a.m.

@InfoSecDJ - Could you do an entire wafer?

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Tim 'mithro' Ansell

@InfoSecDJ - Could you do an entire wafer?

Most probably not :D That said, it'd be interesting to have a look at test tiles and features in scribe lanes that got cut (edited)

Tim 'mithro' Ansell

I would love to host a copy on https://data.wafer.space

I'll give you all the links when I am done with the whole run, feel free to host a copy there

InfoSecDJ

Most probably not :D That said, it'd be interesting to have a look at test tiles and features in scribe lanes that got cut (edited)

I'd assume a mere full reticle would be most of the interesting content? Unless someone considers the edge partials particularly interesting.

InfoSecDJ

Most probably not :D That said, it'd be interesting to have a look at test tiles and features in scribe lanes that got cut (edited)

How about the original masks?

Tim 'mithro' Ansell

How about the original masks?

I could give it a try, though the resolution/magnification will be very low due to the area that needs to be covered. One 1x1 die takes about ~16h to image

Masks are 4x larger ? So 10x magnification of mask is the same as 40x of the die.

9:54 a.m.

But yeah still ... full mask is ~ 40x the area of a chip and then there is like ... 25 of them or so ? That's 1.8 year worth

The tyranny of numbers :D

@InfoSecDJ - I think we worked out that my automated microscope (a Labsmore thing from @digshadow) at PS1 would take roughly like 17 hours to do a mask, which is like one a day.

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9:56 a.m.

@carlfk and @Andrew Wingate started doing some stuff which got uploaded at https://data.wafer.space/jaguar-ps1/pyuscope/data/scan/

Tim 'mithro' Ansell

@InfoSecDJ - I think we worked out that my automated microscope (a Labsmore thing from @digshadow) at PS1 would take roughly like 17 hours to do a mask, which is like one a day.

All depends on the quality+resolution you want to get :)

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InfoSecDJ

All depends on the quality+resolution you want to get :)

Always more!

1

namibj started a thread. 2026-09-07 2:54 p.m.

Hmmmm at 100nm pixel size if running 20 fps (as a Pi5 could, at least with an LED strobe) and 50% overlap in both directions (so each spot gets nominally 4 captures coverage) it's "just" 34 seconds plus no-capture times caused by whatever acceleration limits the motion stage imposes at the ends of the zig-zag scan.

I wonder if we should set up something like https://www.honeypotbot.com/ that esden (1bitsquared) just setup on his discord? (edited)

Home | Honeypot

The official guide to Honeypot, the antispam bot for discord!

1

1

I setup something like that on mine and it's helped a bunch to cut down on spam

7:49 p.m.

not perfect, but catches a lot

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-ocd1/infosecdj_mz_nikpa40x

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1

cc @Tim Edwards

good news, I am through all the samples @Leo Moser (mole99) sent me. browsable images here: http://infosecdj.net/map/#wafer-space if you need single images and/or previews, ping me for download urls.

1

These seem pretty cool - https://makerworld.com/en/models/2819094-field-effect-transistor-models-fet-v2#profileId-3139175

wafer.space at the ORConf sticker table

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1

Leo Moser (mole99)

wafer.space at the ORConf sticker table

Thanks!

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I need one of those Corey McCoreface stickers

Two more samples I got from @Tim 'mithro' Ansell of what I understand to be MPW1 via efabless, if anyone knows what they are or has any other information, please let me know so I can label them appropriately http://infosecdj.net/map/efabless/sky130-mpw1-00010016/infosecdj_mz_nikpa40x http://infosecdj.net/map/efabless/sky130-mpw1-0001001f/infosecdj_mz_nikpa40x

https://github.com/jonahsaunders/IC-Design-Studio/tree/main

GitHub - jonahsaunders/IC-Design-Studio

Contribute to jonahsaunders/IC-Design-Studio development by creating an account on GitHub.

11:21 p.m.

Trying to create an open source Windows IC design toolkit

InfoSecDJ

Two more samples I got from @Tim 'mithro' Ansell of what I understand to be MPW1 via efabless, if anyone knows what they are or has any other information, please let me know so I can label them appropriately http://infosecdj.net/map/efabless/sky130-mpw1-00010016/infosecdj_mz_nikpa40x http://infosecdj.net/map/efabless/sky130-mpw1-0001001f/infosecdj_mz_nikpa40x

InfoSecDJ

Two more samples I got from @Tim 'mithro' Ansell of what I understand to be MPW1 via efabless, if anyone knows what they are or has any other information, please let me know so I can label them appropriately http://infosecdj.net/map/efabless/sky130-mpw1-00010016/infosecdj_mz_nikpa40x http://infosecdj.net/map/efabless/sky130-mpw1-0001001f/infosecdj_mz_nikpa40x

https://drive.google.com/drive/folders/1sWcj8wWxIhtSGrlYJxBpKNhfB_B4lU3j?usp=drive_link

InfoSecDJ

Two more samples I got from @Tim 'mithro' Ansell of what I understand to be MPW1 via efabless, if anyone knows what they are or has any other information, please let me know so I can label them appropriately http://infosecdj.net/map/efabless/sky130-mpw1-00010016/infosecdj_mz_nikpa40x http://infosecdj.net/map/efabless/sky130-mpw1-0001001f/infosecdj_mz_nikpa40x

https://docs.google.com/spreadsheets/d/1PrRxdMPXz41_Eq22dZU_VpVKBZ7o9DWDc6EvHnX-CpY/edit?gid=1961196752#gid=1961196752

SKY130 MPW-001 (MPW-1) tapeout manifest - bit.ly/sky130-mpw1-manife...

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InfoSecDJ

Two more samples I got from @Tim 'mithro' Ansell of what I understand to be MPW1 via efabless, if anyone knows what they are or has any other information, please let me know so I can label them appropriately http://infosecdj.net/map/efabless/sky130-mpw1-00010016/infosecdj_mz_nikpa40x http://infosecdj.net/map/efabless/sky130-mpw1-0001001f/infosecdj_mz_nikpa40x

@InfoSecDJ - https://data.wafer.space/big-storage/sky130-masks/masks.html

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found a wafer shard from Tim :)

Oh and it's "delayered" for you

5:22 p.m.

So internal view of sram.

for the curious: http://infosecdj.net/map/efabless/gf180mcu-gfmpw1-partials/infosecdj_mz_nikpa40x

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is there a way to determine which layers are represented by which colours? this might be useful for something

They don't seem to be in order or all present. You have vias without corresponding metal AFAICT

floating vias

6:24 p.m.

thats a shame tho

@carlfk - https://data.wafer.space/big-storage/sky130-masks

Tim 'mithro' Ansell

@carlfk - https://data.wafer.space/big-storage/sky130-masks

something broke

1:45 a.m.

https://data.wafer.space/big-storage/sky130-masks/mpw-001_CAP2M/mpw-001_CAP2M_slot-001_A1.png

1:45 a.m.

"contains errors"

carlfk

https://data.wafer.space/big-storage/sky130-masks/mpw-001_CAP2M/mpw-001_CAP2M_slot-001_A1.png

I think you'll find the png is just too big to load in a web browser.

2:03 a.m.

@Matt Venn / @Leo Moser (mole99) - How was / is OrConf? Anything I should check out or follow up on?

Tim 'mithro' Ansell

I think you'll find the png is just too big to load in a web browser.

maybe. gimp opened it, but:

2:04 a.m.

carl@notp:~/temp$ display mpw-001_CAP2M_slot-001_A1.png display: Image height exceeds user limit in IHDR

mpw-001_CAP2M_slot-001_A1.png' @ warning/png.c/MagickPNGWarningHandler/1531.
display: Invalid IHDR data

mpw-001_CAP2M_slot-001_A1.png' @ error/png.c/MagickPNGError/1305.

@carlfk - Yeah, claude was complaining it needed to recompile PIL with some type of size numbers increased....

Tim 'mithro' Ansell

@Matt Venn / @Leo Moser (mole99) - How was / is OrConf? Anything I should check out or follow up on?

It was great! Biggest ORConf so far. Well, for one, my talk

https://fossi-foundation.org/orconf/2026#a-look-back-at-two-successful-waferspace-shuttle-runs

Leo Moser (mole99)

It was great! Biggest ORConf so far. Well, for one, my talk

https://fossi-foundation.org/orconf/2026#a-look-back-at-two-successful-waferspace-shuttle-runs

Now I have to go check what you are saying about me

1

@Leo Moser (mole99) - Do you know where I should report the fact that the slides icon on the panel session goes to Olof's talk rather than anything to do with the panel?

Leo Moser (mole99)

It was great! Biggest ORConf so far. Well, for one, my talk

https://fossi-foundation.org/orconf/2026#a-look-back-at-two-successful-waferspace-shuttle-runs

Direct video link for the lazy - https://www.youtube.com/watch?v=ILq8vYjClio

FOSSi Foundation

A Look Back at Two Successful wafer.space Shuttle Runs (Leo Moser)

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Tim 'mithro' Ansell

Direct video link for the lazy - https://www.youtube.com/watch?v=ILq8vYjClio

Thanks.

Tim 'mithro' Ansell

@Leo Moser (mole99) - Do you know where I should report the fact that the slides icon on the panel session goes to Olof's talk rather than anything to do with the panel?

Yes, here: https://github.com/fossi-foundation/fossi-foundation-web

If I can successfully route this, it’ll be a 3-in-1 for a run 2 bringup

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3:44 p.m.

I’m giving one of my RISC-V cores on run 2 128MiB of RAM for.... reasons (edited)

3:44 p.m.

But I gave two other 32-bit CPUs on the die the same pad-out and bus interface as the RISC-V core, so they can all use the same hardware.

Cool!

that route looks pretty tame

(OT meta whatever ) @buttercutter I see your friend request, but hitting "accept "doesn't do anything. and I can't DM you because we are not friends.

https://blog.janestreet.com/protocol-emulator-asic-competition/

Can you design a chip? Announcing the protocol emulator ASIC compet...

1

Tholin

If I can successfully route this, it’ll be a 3-in-1 for a run 2 bringup

I think @asic destroyer might have some hints / tips -- I think he has something similar working on his KIAN-V board from Run #1

kris

is there a way to determine which layers are represented by which colours? this might be useful for something

Not that I know of, which is unfortunate

Tim 'mithro' Ansell

I think @asic destroyer might have some hints / tips -- I think he has something similar working on his KIAN-V board from Run #1

That is my inspiration, except the DRAM controller is off-chip on an FPGA. Though I might take a peek at their DRAM controller RTL.

@Tholin - Anything interest in https://ieeexplore.ieee.org/abstract/document/11683180/ ? CMOS Inverter Standard Cell Library–Design and Characterization Using SKY130 PDK

I can’t access the full thing, but I think I’m also beyond making just inverters.

Tim 'mithro' Ansell

@Tholin - Anything interest in https://ieeexplore.ieee.org/abstract/document/11683180/ ? CMOS Inverter Standard Cell Library–Design and Characterization Using SKY130 PDK

honestly wishing they'd have taken something less trivial like for example a full adder to make their example of, largely because a mere inverter lacks many interactions that require simulation/extraction/design treatment.

Wafer Delay for Run #2

Hi @everyone, we've got some important news to share about Run #2. Good news: we're expecting an initial set of wafers from Global Foundries soon and there are enough wafers for people to get roughly 100-200 dies from this initial batch. These will be diced as normal, with bare die shipping and COB packaging happening soon after. Bad news: the remaining wafers are delayed until sometime in 2027. No exact date yet, but we will update you when we can. We don't expect this delay to have any impact on the deadlines or timeline of Run #3, so please rest assured if you're building a project for that! (edited)

So will there be COB, or we waiting until 2027 for those?

Tholin

So will there be COB, or we waiting until 2027 for those?

i believe that there will be for the initial batch, so no waiting for that

8:19 p.m.

i'll edit the announcement

wafer.space Community #announcements

Wafer Delay for Run #2

Hi @everyone, we've got some important news to share about Run #2. Good news: we're expecting an initial set of wafers from Global Foundries soon and there are enough wafers for people to get roughly 100-200 dies from this initial batch. These will be diced as normal, with bare die shipping and COB packaging happening soon after. Bad news: the remaining wafers are delayed until sometime in 2027. No exact date yet, but we will update you when we can. We don't expect this delay to have any impact on the deadlines or timeline of Run #3, so please rest assured if you're building a project for that! (edited)

Appreciate the update. We're just delighted to be getting any wafers in 2026 and it's a privilege to support you guys as you figure this stuff out. Thanks for everything you're doing.

1

@Tim Edwards - Is https://ieeexplore.ieee.org/abstract/document/11680832 of interest to you?

Tholin

So will there be COB, or we waiting until 2027 for those?

Yes, we will be doing CoB packaging for the die coming back from the first set of wafers right afterwards.

Tim 'mithro' Ansell

@Tim Edwards - Is https://ieeexplore.ieee.org/abstract/document/11680832 of interest to you?

Yes, that's actually pretty interesting; simulating SEUs without having to add circit infrastructure to inject them.

Tim Edwards

Yes, that's actually pretty interesting; simulating SEUs without having to add circit infrastructure to inject them.

@Tim Edwards - BYU have been doing a whole bunch of open source FPGA related stuff for a long time, you should check out their work if you haven't before.

Hi all, I have some extra 1x1 slots on the upcoming run due December. We are looking to sponsor potentially for free the following things: Anything to do with high speed serdes or protocols, or useful analog. Pushes the boundaries of what is known to be possible on this fabrication process. Things that are useful /critical building blocks for the open source silicon ecosystem. AI assisted designs are OK if you have a realistic way of verifying them. (edited)

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7:51 a.m.

Please feel free to reach out if you are interested in making something that might be a fit for those, you can also message @Paul too (edited)

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1

Run #3: 1x1 Slots Running Low

Hi @everyone, we're down to our last couple full-sized slots, so this is the moment to secure your space before they're all gone! Don't worry, there are plenty of half and quarter-sized slots still available, but if you need all the silicon you can get, now is the time to get it. Buy now: crowdsupply.com/wafer-space/gf180mcu-run-3 Thanks for all your support, and happy building waferspace

baragonaru

Hi all, I have some extra 1x1 slots on the upcoming run due December. We are looking to sponsor potentially for free the following things: Anything to do with high speed serdes or protocols, or useful analog. Pushes the boundaries of what is known to be possible on this fabrication process. Things that are useful /critical building blocks for the open source silicon ecosystem. AI assisted designs are OK if you have a realistic way of verifying them. (edited)

I have a fully analog chip layout in the works, but its on a half slot

baragonaru

Hi all, I have some extra 1x1 slots on the upcoming run due December. We are looking to sponsor potentially for free the following things: Anything to do with high speed serdes or protocols, or useful analog. Pushes the boundaries of what is known to be possible on this fabrication process. Things that are useful /critical building blocks for the open source silicon ecosystem. AI assisted designs are OK if you have a realistic way of verifying them. (edited)

Are there any specific circuits you have in mind for this that are missing (edited)

Has everyone heard of the Jane Street challenge released recently? Seems like there's soon gonna be alottt of Foss designs out

1

v

Are there any specific circuits you have in mind for this that are missing (edited)

Some things i'd be specifically interested in sponsoring: high speed computer interfaces, PCIE, gigabit ethernet, DDR memory, graphics. full stack Radios A riscv microcontroller that can plug into a USB port with no external components (on-chip voltage regulators) (tim's idea) I am not sure if all of these are possible, but it would be great to push the boundaries of what is possible on this process. Also anything that could be considered critical to the open silicon ecosystem even if it's a high-risk design (edited)

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v

Has everyone heard of the Jane Street challenge released recently? Seems like there's soon gonna be alottt of Foss designs out

I believe the Jane Street challenges are being made by @anish

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Tim 'mithro' Ansell

I believe the Jane Street challenges are being made by @anish

As in they are part of making the challenge or competing in the challenge?

baragonaru

Some things i'd be specifically interested in sponsoring: high speed computer interfaces, PCIE, gigabit ethernet, DDR memory, graphics. full stack Radios A riscv microcontroller that can plug into a USB port with no external components (on-chip voltage regulators) (tim's idea) I am not sure if all of these are possible, but it would be great to push the boundaries of what is possible on this process. Also anything that could be considered critical to the open silicon ecosystem even if it's a high-risk design (edited)

Regarding graphics would something similar to Espressif's Pixel Processing Accelerator work? Like accelerating Scale Rotate and Mirror operations for various block sizes

It would be super cool to have a fully open IC that is able to do the 433MHz / 900MHz ISM bands like the CC1101 or SX1278 parts. Having a complete Lora stack would probably be of interest to those paranoid off grid type people.

2

@Andrew Wingate - BTW Did you see https://github.com/iic-jku/IIC-OSIC-TOOLS in the past? Any reason you created your own docker container rather than just reuse that?

GitHub - iic-jku/IIC-OSIC-TOOLS: IIC-OSIC-TOOLS is an all-in-one Do...

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported. - iic-jku/IIC-OSIC-TOOLS

Spaghettiman

Regarding graphics would something similar to Espressif's Pixel Processing Accelerator work? Like accelerating Scale Rotate and Mirror operations for various block sizes

Yes this could be relevant

Tim 'mithro' Ansell

@Andrew Wingate - BTW Did you see https://github.com/iic-jku/IIC-OSIC-TOOLS in the past? Any reason you created your own docker container rather than just reuse that?

I didn't see that until after I was done unfortunately.

baragonaru

Yes this could be relevant

@algofoogle (Anton Maurovic) -- Does your graphics accelerator thingy fall into this category?

Probably different for everyone, but for me the tapeout cost isn't the main obstacle, I'm more looking for ways to sponsor my time

So I can work on such thing without having to worry about having to work on billable things instead.

1

Breaking Taps released his video!

https://www.youtube.com/watch?v=q6ytRHaTEXI Congratz @BreakingTaps we've been looking forward to seeing this for a some time! (edited)

Breaking Taps

I designed a microprocessor

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Just finished! Love the format, so much amazing! Thank you for sharing!

baragonaru

Some things i'd be specifically interested in sponsoring: high speed computer interfaces, PCIE, gigabit ethernet, DDR memory, graphics. full stack Radios A riscv microcontroller that can plug into a USB port with no external components (on-chip voltage regulators) (tim's idea) I am not sure if all of these are possible, but it would be great to push the boundaries of what is possible on this process. Also anything that could be considered critical to the open silicon ecosystem even if it's a high-risk design (edited)

You might be able to do analog graphics processing with my chip.

1

urish started a thread. 2026-09-20 2:47 p.m.

I should make videos about my chips, but I’ve made so many, it’d take a lot of videos just to catch up from the beginning.

1

Tholin

I should make videos about my chips, but I’ve made so many, it’d take a lot of videos just to catch up from the beginning.

Even a generalized overview would be awesome!

You can sortof get that here: https://tholin.dev/chip_gallery

1

2:57 p.m.

If my run 3 submission gets accepted into one of the free slots, I’d make a video on it.

2:57 p.m.

Because it exists without the context of my previous tapeouts

i would love to watch (or read!) more about all your chips!

2

https://tholin.dev/custom_silicon/ https://tholin.dev/custom_silicon_two_electric_boogaloo/

1

Tholin

If my run 3 submission gets accepted into one of the free slots, I’d make a video on it.

Haha, selling that one hard ;)

BreakingTaps started a thread. 2026-09-20 4:31 p.m.

Dunno if we mentioned, but the first 6 wafers from Run #2 came back from GF last week and are with the dicing house.

4

1

Tholin

You can sortof get that here: https://tholin.dev/chip_gallery

This is amazing!! How long have you been doing this? Do you do circuit related stuff fulltime?

Is there a way to lift the 6 hour execution time limit on GH actions? Characterizing my SCL now takes longer than 6 hours thanks to mux4.

v

This is amazing!! How long have you been doing this? Do you do circuit related stuff fulltime?

TinyTapeout 2 was at the end of 2022, I think

10:49 a.m.

Coming up on 4 years

Tholin

Is there a way to lift the 6 hour execution time limit on GH actions? Characterizing my SCL now takes longer than 6 hours thanks to mux4.

I don't think there is, but there's no restriction on running multiple jobs in parallel

I want to add more combinatorial cells to my SCL, I just need to know which ones

@Simo6572 Do you by any chance already have a list of useful cells handy?

Leo Moser (mole99)

@Simo6572 Do you by any chance already have a list of useful cells handy?

Looking to my netlist ( ! Means NOT): !((A+B)C) !((A+B)(C+D)) !(!A + B) !(!A!BC) !(!A!BCD) !(!A!B!CD) (A+B)CD (AB)+(CD)+(E*F) Inverting 2x1 MUX Inverting 4x1 MUX Instead, if you are interesting to know the gap VS the entire commercial library, I can ask AI to do the analysis but it is surely much bigger

Simo6572

Looking to my netlist ( ! Means NOT): !((A+B)C) !((A+B)(C+D)) !(!A + B) !(!A!BC) !(!A!BCD) !(!A!B!CD) (A+B)CD (AB)+(CD)+(E*F) Inverting 2x1 MUX Inverting 4x1 MUX Instead, if you are interesting to know the gap VS the entire commercial library, I can ask AI to do the analysis but it is surely much bigger

Thank you! No need to ask AI, we already have SCLs from other open-source PDKs to compare to. I'm sure this list is already useful to Tholin.

Tholin

TinyTapeout 2 was at the end of 2022, I think

You are an extremely fast learner, and very inspiring

I’m actually struggling to add more cells to my SCL currently. I’ve got layouts done for oa21_2 and oa21_4 fully done and characterized, but yosys is not using them correctly and synthesizing bad logic unless I remove them from the liberty file. I’ve checked those files a million times, line by line, and all is fine, but yosys is refusing to use them correctly and I have no idea why.

baragonaru

Some things i'd be specifically interested in sponsoring: high speed computer interfaces, PCIE, gigabit ethernet, DDR memory, graphics. full stack Radios A riscv microcontroller that can plug into a USB port with no external components (on-chip voltage regulators) (tim's idea) I am not sure if all of these are possible, but it would be great to push the boundaries of what is possible on this process. Also anything that could be considered critical to the open silicon ecosystem even if it's a high-risk design (edited)

I propose including a fixed (non-shorted-out) version of what I submitted to ttgf0p3 ; it's a 2~3 GHz quadrature VCO, inductorless. A minor addition of some PMOS I can grab sizing for later this week if requested would allow it to clock down and sustain oscillation to on the order of 100 MHz (and less though that'll be a little less trivial to pull off). If pins/space is available, not that it's large at all, but having it in would validate the VCO for a multi-gigabit SerDes.

2

Tholin

I’m actually struggling to add more cells to my SCL currently. I’ve got layouts done for oa21_2 and oa21_4 fully done and characterized, but yosys is not using them correctly and synthesizing bad logic unless I remove them from the liberty file. I’ve checked those files a million times, line by line, and all is fine, but yosys is refusing to use them correctly and I have no idea why.

Share them with @Simo6572 maybe they actually have some insight as to what's weird about them to cause them to not be picked for reasons other than Yosys being stupid/abc not doing passes that'd really spur them on?

They are picked

3:03 p.m.

And used incorrectly

3:03 p.m.

The resulting netlist is broken

3:04 p.m.

I don’t know yosys thinks they are

oh

3:04 p.m.

delete the timing info from the liberty entries and visually diff them against their brethen from one of the open SCLs that has one of them and has yosys not choke on it?

The fab SCL doesn’t have oa21 cells

3:07 p.m.

Actually, it doesn’t have any oa or ao cells

1

3:07 p.m.

Huh

baragonaru

Some things i'd be specifically interested in sponsoring: high speed computer interfaces, PCIE, gigabit ethernet, DDR memory, graphics. full stack Radios A riscv microcontroller that can plug into a USB port with no external components (on-chip voltage regulators) (tim's idea) I am not sure if all of these are possible, but it would be great to push the boundaries of what is possible on this process. Also anything that could be considered critical to the open silicon ecosystem even if it's a high-risk design (edited)

I have a pretty concrete concept/approach proposal for a "muxed e-test" that'd work with a slightly fancier multimeter than the COB bond test jig already in use, and would utilize a dense analog switch (transmission gate) based bus to connect a variety (think 200 on a full slot) of DUTs in 4-wire like "kelvin" connectivity to external pins to have separate sense and drive wires for all the contact/via/"pin" zones of the DUTs; to be used with e.g. Xyce predictor based selection of what operating points to measure under DC or near-DC conditions, in order to fine-tune the SPICE model of e.g. an SCL and use the 1000 such dies via their cheap COB bonding and a simple test jig (just needs decent volt/current meters behind for good measurements) to get statistically significant data on mismatch across similar structures right besides one another, across reticles on a wafer, and across wafers of a lot. I'd think it could be scripted with librelane I just don't have the time to do that myself; in lieau of that it could be scripted with klayout (or magic) as it's essentially just a bus with switches underneath DUTs on one side and a digital decoder logic on the other side that just allows for externally selecting which DUT to mux to the bus. Just a decoder into one-hot select bits across the DUT slots should suffice. DUTs would be SCL cells of sufficient notability, and a bunch of primitives that are lacking foundry open-source e-test coverage (e.g. there's no data on vias/contacts, there's no coverage for thin oxide native nmos at all, there's no coverage for (admittedly kinda DRC-breaking though IMO that's ERC domain and should be waived for at least test structures if modeling is good enough) short channel native NMOS, a LOT of devices lack mismatch characterization (e.g. shottkey diodes are just a start)). No dynamic behavior intended. I would like some latchup-type structures if they can be wired to be provoked into latchup with that analog mux, to get at least a hint of e-test coverage for such behavior as it ma not be catastrophic if the chip is prevented from melting itself via teh ensuing power dissipation.

1

Tholin

The fab SCL doesn’t have oa21 cells

Doesn't have to be that fab SCL.

3:21 p.m.

Can literally be an OSU IHP library for all it matters

3:26 p.m.

For clarification I can guide someone who can write code well enough to read the docs and figure out how to do that scripting; they don't have to understand how the structures work but they should understand enough of ASIC design to grasp how the routing decisions for such matrix/bus structures can be drawn for density and still having reasonably decent signal quality. Don't want the modeling of the matrix to dominate the measurement uncertainty and 1/f noise modeling....

Okay, got it. I can add cells to my SCL again!

4:55 p.m.

Something about either cocotb or iverilog changed AGAIN and AGAIN broke my gate-level verification setup to test sample flow outputs on my SCL

4:55 p.m.

Cells were good the whole time

4:55 p.m.

Unrelated: @namibj you suggested I should shrink the FETs in my charger IC’s power FET macro, right? They’re 2um in length right now, but its not too late for me to bring that down to 1um.

namibj

I have a pretty concrete concept/approach proposal for a "muxed e-test" that'd work with a slightly fancier multimeter than the COB bond test jig already in use, and would utilize a dense analog switch (transmission gate) based bus to connect a variety (think 200 on a full slot) of DUTs in 4-wire like "kelvin" connectivity to external pins to have separate sense and drive wires for all the contact/via/"pin" zones of the DUTs; to be used with e.g. Xyce predictor based selection of what operating points to measure under DC or near-DC conditions, in order to fine-tune the SPICE model of e.g. an SCL and use the 1000 such dies via their cheap COB bonding and a simple test jig (just needs decent volt/current meters behind for good measurements) to get statistically significant data on mismatch across similar structures right besides one another, across reticles on a wafer, and across wafers of a lot. I'd think it could be scripted with librelane I just don't have the time to do that myself; in lieau of that it could be scripted with klayout (or magic) as it's essentially just a bus with switches underneath DUTs on one side and a digital decoder logic on the other side that just allows for externally selecting which DUT to mux to the bus. Just a decoder into one-hot select bits across the DUT slots should suffice. DUTs would be SCL cells of sufficient notability, and a bunch of primitives that are lacking foundry open-source e-test coverage (e.g. there's no data on vias/contacts, there's no coverage for thin oxide native nmos at all, there's no coverage for (admittedly kinda DRC-breaking though IMO that's ERC domain and should be waived for at least test structures if modeling is good enough) short channel native NMOS, a LOT of devices lack mismatch characterization (e.g. shottkey diodes are just a start)). No dynamic behavior intended. I would like some latchup-type structures if they can be wired to be provoked into latchup with that analog mux, to get at least a hint of e-test coverage for such behavior as it ma not be catastrophic if the chip is prevented from melting itself via teh ensuing power dissipation.

I like both of these, can they be the same chip?

1

Anyone able to access https://ieeexplore.ieee.org/abstract/document/11684413 and then understand if it is doing anything interesting at all?

This work presents a fully automated methodology for generating cryogenic BSIM4 models for the open-source Sky130 technology using experimental transistor measurements from the NIST 4 K dataset. The proposed flow combines physics-based parameter initialization using SEKV-E with iterative differential-evolution optimization driven by NGSPICE simulations, enabling scalable geometry-specific model generation without manual tuning.

Bold highlighting is mine. As I don't have access, also don't know if they have published their code or if it depends on any actual proprietary tooling.

1

Tim 'mithro' Ansell

Anyone able to access https://ieeexplore.ieee.org/abstract/document/11684413 and then understand if it is doing anything interesting at all?

This work presents a fully automated methodology for generating cryogenic BSIM4 models for the open-source Sky130 technology using experimental transistor measurements from the NIST 4 K dataset. The proposed flow combines physics-based parameter initialization using SEKV-E with iterative differential-evolution optimization driven by NGSPICE simulations, enabling scalable geometry-specific model generation without manual tuning.

Bold highlighting is mine. As I don't have access, also don't know if they have published their code or if it depends on any actual proprietary tooling.

Sorry, I don't pay IEEE dues

But surely one of us there does.

1

Tim 'mithro' Ansell

Anyone able to access https://ieeexplore.ieee.org/abstract/document/11684413 and then understand if it is doing anything interesting at all?

This work presents a fully automated methodology for generating cryogenic BSIM4 models for the open-source Sky130 technology using experimental transistor measurements from the NIST 4 K dataset. The proposed flow combines physics-based parameter initialization using SEKV-E with iterative differential-evolution optimization driven by NGSPICE simulations, enabling scalable geometry-specific model generation without manual tuning.

Bold highlighting is mine. As I don't have access, also don't know if they have published their code or if it depends on any actual proprietary tooling.

i read it, i can't find the authors code, but i did find the model they were trying to improve upon here https://github.com/Mauricio-xx/IceMOS_sky130/tree/main

GitHub - Mauricio-xx/IceMOS_sky130: Open ToolBox to enable PDK cali...

Open ToolBox to enable PDK calibration for SKY130 open PDK - Mauricio-xx/IceMOS_sky130

7:05 a.m.

the paper you sent compared to iceMOS error. apparently this is more accurate in strong inversion (edited)

Simo6572

Looking to my netlist ( ! Means NOT): !((A+B)C) !((A+B)(C+D)) !(!A + B) !(!A!BC) !(!A!BCD) !(!A!B!CD) (A+B)CD (AB)+(CD)+(E*F) Inverting 2x1 MUX Inverting 4x1 MUX Instead, if you are interesting to know the gap VS the entire commercial library, I can ask AI to do the analysis but it is surely much bigger

A bunch of these are already in the SCL, but some aren’t. The list I want to get through now is:

oai22
oa22
~~nand3b~~
~~nand3bb~~
nand4b
nand4bb
nand4bbb
aoi222
ao222

(edited)

Tholin

A bunch of these are already in the SCL, but some aren’t. The list I want to get through now is:

oai22
oa22
~~nand3b~~
~~nand3bb~~
nand4b
nand4bb
nand4bbb
aoi222
ao222

(edited)

Interesting to know, I don't understand why Yosys didn't select them do create my netlist if a subset of them was already in

baragonaru

I like both of these, can they be the same chip?

Sure, the muxed e-test has spare pads

Already got the first two done and verified

Hello friends! Excited to be here, we will probably be ordering some spots on run 3!

We make a compiler so we have ~8 designs we are working on taping out. A memory controller, our own spatial fabric similar to a CGRA, a HFT workload example, and llm inference stuff too. Excited to join and be a part of the community, we will open source some of our designs as well I think! We had things signoff clean for the Sky130 process using the golden shuttle files and such, but I'm working on adding GF180 compiler support.

1

5:34 p.m.

We're in Santa Clara area so let me know if anyone else is around and let's grab some coffee sometime! We also are planning to make friends with folks at GF stopping by their office in person sometime. Anyways, hope y'all have a nice day, looking forward to getting to know y'all. Have a feeling I'll be stopping by frequently haha

https://www.sprind.org/en/actions/challenges/ai-native-chip-design

SPRIND | AI-Native Chip Design

We need pioneering teams for whom speed is everything. Teams that make tomorrow’s chip development as effortless as today’s software engineering. Apply by November 30, 2026.

2

Tim 'mithro' Ansell

Anyone able to access https://ieeexplore.ieee.org/abstract/document/11684413 and then understand if it is doing anything interesting at all?

This work presents a fully automated methodology for generating cryogenic BSIM4 models for the open-source Sky130 technology using experimental transistor measurements from the NIST 4 K dataset. The proposed flow combines physics-based parameter initialization using SEKV-E with iterative differential-evolution optimization driven by NGSPICE simulations, enabling scalable geometry-specific model generation without manual tuning.

Bold highlighting is mine. As I don't have access, also don't know if they have published their code or if it depends on any actual proprietary tooling.

I'd aim for a more modern model than bsim4...... notably it's source-relative which makes it really ugly when you try to model multi-finger structures without pronounced diffusiion regions between the fingers (such as approximation models for octagonal annular transistors as an example: gotta model the significant width difference between the inner border and the outer border of gate poly). But yeah, I had planned similar approach just with either a more modern bsim or with PSP 107. Timeline for that was looking forward to summer next year.

Tim 'mithro' Ansell

https://www.sprind.org/en/actions/challenges/ai-native-chip-design

>Bundesagentur

Run #3: Early Bird Deadline + 1x1 Slots Gone!

All of our full-sized slots are gone! Thank you @everyone for supporting us waferspace

❤️ Plenty of half and quarter-sized slots are still up for grabs, so there is still a chance to join Run #3 if you haven't already. Speaking of which... Early bird pricing ends in a week! You have until 30 September 2026 23:59 AoE to lock in the discounted price ($2/die for the quarter slot and $4/die for the half slots) and save money on your next tape out. Don't wait until the very last minute - they might be gone by then! Get your slot here: crowdsupply.com/wafer-space/gf180mcu-run-3

Starter question: I am installing the template and librelane on an Ubuntu 24.04.4 LTS VM. I am wondering why so many Nix packages are compiled from source. The nix-shell runs now for probably an hour or more.

Do you have the fossi foundation nix cache enabled ?

not explicitly, just did as described in the README.

3:45 p.m.

Or maybe I had from a former librelane installation on the same machine.

Which README ?

I think I did install according to the nix setup as described in the LibreLane docu. Never mind, I will give it a new try from scratch.

Gave it a try on Ubuntu on ARM64 (as I have a Mac) and got the following error:

error: Package ‘ghdl-bin-5.1.1’ in /nix/store/amc3kqk26hj1rkcpkv2b9rqpv17wf8j6-source/nix/ghdl-bin.nix:114 is not available on the requested hostPlatform:
         hostPlatform.system = "aarch64-linux"

1

Martin Schoeberl

Gave it a try on Ubuntu on ARM64 (as I have a Mac) and got the following error:

error: Package ‘ghdl-bin-5.1.1’ in /nix/store/amc3kqk26hj1rkcpkv2b9rqpv17wf8j6-source/nix/ghdl-bin.nix:114 is not available on the requested hostPlatform:
         hostPlatform.system = "aarch64-linux"

Ohhh, yeah, that's much less surprising. Go compile or set the VM to be x86_64.

But I am running on an ARM? How can I force nix to compile?

Martin Schoeberl

But I am running on an ARM? How can I force nix to compile?

Don't use the -bin of ghdl? Or set your Mac's Linux VM runtime to give you an x86 VM, the MAC processors have extra modes to allow very efficient emulation.

Martin Schoeberl

Gave it a try on Ubuntu on ARM64 (as I have a Mac) and got the following error:

error: Package ‘ghdl-bin-5.1.1’ in /nix/store/amc3kqk26hj1rkcpkv2b9rqpv17wf8j6-source/nix/ghdl-bin.nix:114 is not available on the requested hostPlatform:
         hostPlatform.system = "aarch64-linux"

https://github.com/librelane/librelane/issues/859

GHDL Build Fails on aarch64-linux · Issue #859 · librelane/librelane

Description Hi Everyone! Today, I tried to run the nix-shell for the ihp-sg13g2 template repo: https://github.com/IHP-GmbH/ihp-sg13g2-librelane-template Unfortunately, during the build process, GHD...

I did not use the bin, I am just installing with nix and it should compile from source if it does not find the package. Going for a x86 on top of ARM. This is brutally slow (I have done it with Windows 11 for Vivado).

See what that 3.X is they mention in the response to that issue.

Is there a way to skip GHDL in the LibreLane installation? I don't plan to use VHDL.

Martin Schoeberl

Is there a way to skip GHDL in the LibreLane installation? I don't plan to use VHDL.

Should be. Have you considered running librelane directly on macos?

namibj

Should be. Have you considered running librelane directly on macos?

What do you mean? Yes, I have a setup to run plain LibreLane on my Mac (also chipIgnite Sky130 work), but the version that is pinned for the wave.space template gives me trouble.

https://github.com/librelane/librelane/issues/674 ?

GHDL not available on aarch64 platforms · Issue #674 · librelane/...

Issue originally created by fred-corp on 2025-02-19T22:58:39Z Description When trying to use a VHDL source with the --flow VHDLClassic argument, I get the following Yosys error : ERROR: Can't l...

Martin Schoeberl

What do you mean? Yes, I have a setup to run plain LibreLane on my Mac (also chipIgnite Sky130 work), but the version that is pinned for the wave.space template gives me trouble.

You can run it on Darwin or on Linux; but it seems Linux with arm64 isn't available.

wafer.space Community #announcements

Run #3: Early Bird Deadline + 1x1 Slots Gone!

All of our full-sized slots are gone! Thank you @everyone for supporting us waferspace

❤️ Plenty of half and quarter-sized slots are still up for grabs, so there is still a chance to join Run #3 if you haven't already. Speaking of which... Early bird pricing ends in a week! You have until 30 September 2026 23:59 AoE to lock in the discounted price ($2/die for the quarter slot and $4/die for the half slots) and save money on your next tape out. Don't wait until the very last minute - they might be gone by then! Get your slot here: crowdsupply.com/wafer-space/gf180mcu-run-3

Are the sponsored 1x1 slots also gone or...

Martin Schoeberl

What do you mean? Yes, I have a setup to run plain LibreLane on my Mac (also chipIgnite Sky130 work), but the version that is pinned for the wave.space template gives me trouble.

This reads more like a nix packet manager not having the packet for arm rather than really a librelane issue. That said, I don't understand nix that well so I might not be of huge help here, but I suspect it might be pulled by cocotb. Which version of librelane did you have running previously ? Was it a +3.0 version ? (edited)

Essen

This reads more like a nix packet manager not having the packet for arm rather than really a librelane issue. That said, I don't understand nix that well so I might not be of huge help here, but I suspect it might be pulled by cocotb. Which version of librelane did you have running previously ? Was it a +3.0 version ? (edited)

I can install the same LibreLane version (the one pinned to the template: LibreLane v3.1.0.dev2) with nix under MacOS with ARM64. I just have trouble running it (an issue with KLayout at some step). Therefore, I was trying the Linux ARM route.

1

namibj

https://github.com/librelane/librelane/issues/674 ?

But that issue pops up when trying to run a VHDL file through Yosys, which I am not trying to do. I think I do not need GHDL in my LibreLane flow.

namibj

Should be. Have you considered running librelane directly on macos?

Yes, I did, but I have following issue: https://github.com/wafer-space/gf180mcu-project-template/issues/72

Issues under MacOS · Issue #72 · wafer-space/gf180mcu-project-tem...

Running SLOT=0p5x0p5 make librelane Leads to the following error message (about 150000 times) in antenna checking (nn-klayout-antanna): libc++abi: terminating due to uncaught exception of type std:...

No promises but I own a few macs ... so in case you guys are in a pinch I can give it a shot @Leo Moser (mole99) .

1

Also @Martin Schoeberl which OSX version are you using, and which mac generation ? (edited)

Essen

Also @Martin Schoeberl which OSX version are you using, and which mac generation ? (edited)

26.6.2, M1

1

@Egor Lukyanchenko - Do you have any details about the efuse designs on the latest tape outs?

@Martin Schoeberl Let me address your two issues. 1. Nix is recompiling the binaries This should not happen if you have the FOSSi Nix cache set up. Please follow the installation instructions at https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html, making sure you set up https://nix-cache.fossi-foundation.org as an additional Nix cache. You can verify that the Nix cache has been set up correctly by starting a Nix shell with LibreLane (nothing should recompile):

$ nix shell github:librelane/librelane
$ librelane --smoke-test

2. ghdl-bin is not available for aarch64-linux The ghdl-bin package (the VHDL simulator) is only available for x86_64-linux and aarch64-darwin. That is unfortunately a limitation of GHDL as it only targets these platforms afaik: https://github.com/ghdl/ghdl/releases/tag/v6.0.0 ghdl-bin is required by wafer.space because the Nix flake in the gf180mcu-project-template includes cocotb, and cocotb requires ghdl-bin during the check phase. We can try to workaround this problem: You can simply remove the cocotb package from the Nix flake: https://github.com/wafer-space/gf180mcu-project-template/blob/0de7e394337a1f7f5303ac7a3681bf2481b58176/flake.nix#L71 This should allow you to enable the Nix shell and run LibreLane. However, you won't be able to run any simulations with cocotb. Another workaround would be to disable the check phase in cocotb and remove ghdl-bin when the platform is aarch64-linux. Of course, then we can't be sure that cocotb will work as expected, but it will probably be fine. Let me know if you would like to give this a try.

Leo Moser (mole99)

@Martin Schoeberl Let me address your two issues. 1. Nix is recompiling the binaries This should not happen if you have the FOSSi Nix cache set up. Please follow the installation instructions at https://librelane.readthedocs.io/en/stable/installation/nix_installation/index.html, making sure you set up https://nix-cache.fossi-foundation.org as an additional Nix cache. You can verify that the Nix cache has been set up correctly by starting a Nix shell with LibreLane (nothing should recompile):

$ nix shell github:librelane/librelane
$ librelane --smoke-test

2. ghdl-bin is not available for aarch64-linux The ghdl-bin package (the VHDL simulator) is only available for x86_64-linux and aarch64-darwin. That is unfortunately a limitation of GHDL as it only targets these platforms afaik: https://github.com/ghdl/ghdl/releases/tag/v6.0.0 ghdl-bin is required by wafer.space because the Nix flake in the gf180mcu-project-template includes cocotb, and cocotb requires ghdl-bin during the check phase. We can try to workaround this problem: You can simply remove the cocotb package from the Nix flake: https://github.com/wafer-space/gf180mcu-project-template/blob/0de7e394337a1f7f5303ac7a3681bf2481b58176/flake.nix#L71 This should allow you to enable the Nix shell and run LibreLane. However, you won't be able to run any simulations with cocotb. Another workaround would be to disable the check phase in cocotb and remove ghdl-bin when the platform is aarch64-linux. Of course, then we can't be sure that cocotb will work as expected, but it will probably be fine. Let me know if you would like to give this a try.

Hi @Leo Moser (mole99) thank you for your detailed reply. As Tjark found a workaround for the Mac issue (Qt in KLayout has concurrency problems on MacOS) to set workers to 1, I am back being able to run native LibreLane for wafer.space on my Mac. I can drop my ARM Linux experiment. All set and looking forward to our first tapeout at wafer.space.

1

Testing Dies

Thousands of dies are produced from each run, but how do we actually know they're good? What can we test for, and how? Thanks to the community and the work of @lauri4332, we may have a solution. Learn more: crowdsupply.com/wafer-space/gf180mcu-run-3/updates/testing-dies -# P.S. This doesn't contain all the recent changes to die testing, that'll come in a future update!

Testing Dies

With thousands of dies being produced in each run, and with every project being unique, how can we make sure that you get the best results and yield? There's no single "does it work" check that fits everyone, so it turns testing into an interesting puzzle to solve. What do we test for?

2

1

Tim 'mithro' Ansell

@Egor Lukyanchenko - Do you have any details about the efuse designs on the latest tape outs?

@Tim 'mithro' Ansell Unfortunately I'm not aware of any designs containing efuse apart from our Run 1 testchip. The only one who contacted me regarding using efuses in their design was Leo, but I advised him against it because his design was 3.3V.

@Egor Lukyanchenko - I was under the impression that the Zedulo group had used them?

Egor Lukyanchenko

@Tim 'mithro' Ansell Unfortunately I'm not aware of any designs containing efuse apart from our Run 1 testchip. The only one who contacted me regarding using efuses in their design was Leo, but I advised him against it because his design was 3.3V.

Do you mean the Google Run #1 or the wafer.space Run #1 ?

Tim 'mithro' Ansell

@Egor Lukyanchenko - I was under the impression that the Zedulo group had used them?

No, not for the Run 2 designs.

Tim 'mithro' Ansell

Do you mean the Google Run #1 or the wafer.space Run #1 ?

WS Run 1.

@Egor Lukyanchenko - Do you have test data from Run #1 ?

@Tim 'mithro' Ansell I've reported the preliminary test results for the WS Run 1 testchip here some time ago. Basically all efuses blocks tested worked at 5V as intended. But the test was performed for one chip only which is definitely not enough. Since then not much changed as Zedulo had some packaging and chip bringup issues and they are busy with other things now, so they are not planing to run more efuse tests. But I have a couple of chips at my personal disposal now and am preparing a test board for them currently. So I hope to have a bit more representative data in comming weeks.

If we manage to get the harness structure for the muxed-etest ready, I would given those circumstances definitely suggest including a thin and a thick oxide efuse structure (or more than one even) for such testing.... To appropriately plan supporting such testing as efuse writing is naturally dynamic; can someone share an understanding of the timescales that are involved in the process?

Egor Lukyanchenko

@Tim 'mithro' Ansell I've reported the preliminary test results for the WS Run 1 testchip here some time ago. Basically all efuses blocks tested worked at 5V as intended. But the test was performed for one chip only which is definitely not enough. Since then not much changed as Zedulo had some packaging and chip bringup issues and they are busy with other things now, so they are not planing to run more efuse tests. But I have a couple of chips at my personal disposal now and am preparing a test board for them currently. So I hope to have a bit more representative data in comming weeks.

Would putting them on another wafer.space run where they are mounted on the standard wafer.space CoB be useful / helpful?

Tim 'mithro' Ansell

Would putting them on another wafer.space run where they are mounted on the standard wafer.space CoB be useful / helpful?

Sure, that will allow to perform much better characterization in the future.

Any news on the run #2 wafers ? Diced ?

1

@Tim 'mithro' Ansell ^ (sorry for ping)

tnt

Any news on the run #2 wafers ? Diced ?

Not yet, they are expect to be back from dicing at the end of this week.

2

Did they have to thin them in the end or did they manage without back grinding ?

tnt

Did they have to thin them in the end or did they manage without back grinding ?

Not sure.

1

10:50 a.m.

@tnt - Poke me again about the etest data as well

Exciting!

11:33 a.m.

I get to find out how my die looks

11:33 a.m.

I’d like to get microscope pics, even quick ones, of the palette in one corner of my die, so I can forward that to my artists asap.

I’ve now ordered everything I need for the bring-up

1:14 p.m.

I’m ready

Run #3: Last 48 Hours for Early Bird Discount

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1

@Tim 'mithro' Ansell I've been busy developing an open source online makerspace the last decade and was wondering if wafer space would like to check it out. It will allow makers to build blueprints around your products and have them linked directly to your solutions. Hit me a PM if you wish to know more

Monster commit to my SCL, probably done for now

2

1

9:30 p.m.

I may do nor3b and nor3bb, but that might not do much for reasons.

9:30 p.m.

I see the fab SCL has or and and with 3 and 4 inputs. Maybe.

9:30 p.m.

I do almost have an orthogonality going in my SCL where every inverting cell has a non-inverting counterpart.

More!

1

12:18 a.m.

or3, or4 tomorrow

when will the next shuttle after this one be?

Tetrahedron

when will the next shuttle after this one be?

expect final GDS deadline 4 weeks after shipping of this run's dies. More concrete information should come once this run's deadline has passed.

1:48 a.m.

I have a feeling that maybe the reduced mask count option could come up for intermediate runs and/or an overlapping quarterly schedule could come depending on how steady demand remains.

Tetrahedron

when will the next shuttle after this one be?

Still working that out, hopefully have an announcement soon.

Alright, I’m done

1

1:01 p.m.

If anyone wants to tape out a SoC or something with this now to try it, you may

1:01 p.m.

Highly doubtful I will add any more cells now

Tholin

Highly doubtful I will add any more cells now

TSPC-DFF?

A what?

Tholin

A what?

True single phase clock data flip flop.

Tholin

A what?

3:18 p.m.

It.... does get more intense:

Those are iiuc a major point of blame for microprocessors broadly gaining "minimum clock speed" requirements some 20~30 years ago.

This is just a improved dynamic DFF

3:52 p.m.

I’ve taped out some of those on run 2

3:52 p.m.

The fab SPICE models are not advanced enough to truly simulate them

3:53 p.m.

I have no idea if they work or what the minimum clock speed will be

A Need for Speed: @tholin's Own Standard Cell Library

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A Need for Speed: Tholin's Own Standard Cell Library

Performance -- an elusive metric that is influenced by everything the chip consists of, and more. The HDL that defines it, the way it is logically laid out, to the tiniest splattering of a chemical on the wafer, and the environment the chip lives in. How far can you go to chase speed?

Tholin

The fab SPICE models are not advanced enough to truly simulate them

huh????

Yeah. They don’t accurately model the gate capacitance and relevant leakage currents.

6:33 p.m.

Whenever I try to sim a dynamic DFF, the gates hold a charge indefinitely

pretty sure with that wirng there most of the leakage isn't through the gate oxide, at least on these relatively thick oxide devices

Tholin

Whenever I try to sim a dynamic DFF, the gates hold a charge indefinitely

you need to set the tolerances of the spice solving to reflect the finesse of the situation.

6:35 p.m.

(Also if you run it through Xyce you can go for fast-forward through like a literal second of try-and-hold-it with the accuracy cranked really sensitive.)

6:36 p.m.

Due to the way it handles the timestemps for you; though I guess for that situation with just a start and then developing towards a cutoff end-time, the flexible dynamic breakpoint insertion of Xyce doesn't actually trigger so ngspice should be just fine.

Where exactly do you get that they don't model gate capacitance ???

accurately But yeah, the plots I've seen for gf180mcuD aren't bad for the mainstream nmos and pmos transistors.

6:39 p.m.

They're not perfect throughout but it doesn't feel like it'd give wrongful understanding regarding the viability or lack thereof for a particular TSPC-DFF cell design to fit into the SCL.

Leakage also usually has a very very wide variance, several orders of magnitude between min and max ... so to estimate the min frequency you need to do the math yourself rather than rely on sim. (edited)

PCE exists for a reason; something as contained as a singular 5T/6T/9T TSPC-DFF should actually manage to not hit any of the curse-of-dimensionality complications involved here.

6:41 p.m.

(OFC assuming that is covered by the statistical process variation equations coded into the SPICE model deck.)

6:46 p.m.

(Now I want to figure out how exactly to effectively realize a chopper functionality to use in place of the default passive kelvin-connection-to-via-to-DUT, for allowing measurements of leakage current of a DUT at least a few orders of magnitude below the leakage of the analog MUX between the meter and the entire array of DUTs on the die... there gotta be some way to pull it off, I guess.... I hope.... but that sounds like a task for after a good night of sleep.)

Tholin

If anyone wants to tape out a SoC or something with this now to try it, you may

I gave this a quick go on the run2 version of TinyQV. Standard cell area went down from 582939 to 574317 um^2, so down ~1.5%. fmax before detailed routing up from 66.23 to 74.11MHz, so nearly 12% faster. Very nice!