wafer.space Community

Tim 'mithro' Ansell

Only Al bonds at the moment. @stuart is your person for custom wire bonding contracts.

We've now got a partner who can do gold wire bonding - not the stud bumping though.

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Does someone know if we can have core_VDD > IO_VDD when using the ocd IO? (edited)

Aside from the totally fair objection of "wtf are you doing?" is there anything that would technically prevent me from doing this, such as a diode between core_vdd and io_vdd?

No you can't

5:15 p.m.

(1) There is a parasitic body diode. (2) level converters are not the same to up convert or down convert ... so that wouldn't work anyway.

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tnt

(1) There is a parasitic body diode. (2) level converters are not the same to up convert or down convert ... so that wouldn't work anyway.

Thanks tnt

(edited)

I was reading the PDK documentation for our IO cells a few days ago, and they mention we don't have circuit under the pad on the IO cells in order to comply with the restrictions of the 3 metal layer process (gf180mcuA). So since we are targeting mcuD does this mean there is an opportunity to shorten the io pads by as much as 75um if they where reworked ?

The bond pad is non-CUP due to design manual restriction on 3LM.

(edited)

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Given the trouble with bonding I'm not sure I would go to CUP ...

Tim Edwards

See https://github.com/fossi-foundation/frigate_analog. Basically a field-programmable analog array with DACs, ADCs, instrumentation amplifiers, temperature sensor, etc., etc. Hard to port from sky130 to another process, but I would like to do that for GF180MCU and IHP sg13g2 eventually.

Did this get ported to GF180?

@Archit3ch : No, that did not get ported to GF180. The Chipalooza challenge is a step in that direction.

Essen started a thread. 2026-09-04 2:30 p.m.

namibj

You don't happen to have the skills it takes to figure decently efficient hyperparameters for letting Xyce simulate up to a couple mm^2 of gf180mcuD PEX extraction, or do you? I lack the background to know how to tune the bunch of solver options and solver choices offered

I'm just seeing it being highly stalling on memory with also sadly substantial lacks in reasonable prefetching behavior (it's nowhere near 30% bandwidth utilization and hovers around 0.02~0.05 IPC... Yeah it's bad.)

I have a few ideas... Not at that scale and not with real Xyce models though.

Archit3ch

I have a few ideas... Not at that scale and not with real Xyce models though.

Great. Let's chat later starting in like 2 hours from now, or up to a couple hours later than that?

Essen

I was reading the PDK documentation for our IO cells a few days ago, and they mention we don't have circuit under the pad on the IO cells in order to comply with the restrictions of the 3 metal layer process (gf180mcuA). So since we are targeting mcuD does this mean there is an opportunity to shorten the io pads by as much as 75um if they where reworked ?

The bond pad is non-CUP due to design manual restriction on 3LM.

(edited)

CUP isn't allowed for wedge bonds iirc even at more layers.

namibj

Great. Let's chat later starting in like 2 hours from now, or up to a couple hours later than that?

I'm travelling without a laptop. Currently on the metro. I can share a 1000-foot plan.

@Tholin Check out your WSLG design in high resolution: https://infosec.exchange/@infosecdj/117213266219165204 Dmitry is working through the dies I sent him, more to follow soon

DJ🌞:donor: (@infosecdj@infosec.exchange)

Hello #NakedDieFriday fans, hope you did not miss me too much. Here is this week's eye candy for you. Supplied by good folks at wafer.space/ was a batch of die samples from their first production run. Here is one of them -- a die-sized doodle of their logo. It is open source too: github.com/89Mods/ws-logo-die There is circuitry there apart from the logo, but the project readme does not say what it does. :-) Full-res map: infosecdj.net/map/wafer-space/…

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Archit3ch

I'm travelling without a laptop. Currently on the metro. I can share a 1000-foot plan.

I was thinking maybe a discord voice call whenever convenient for you within the approximate time frame I mentioned?

3:59 p.m.

Add me (discord friend; but let me know so here if you do) if you want btw. (edited)

namibj

CUP isn't allowed for wedge bonds iirc even at more layers.

https://discord.com/channels/1361349522684510449/1545289242417307678/1545442323041886250

Leo Moser (mole99)

@Tholin Check out your WSLG design in high resolution: https://infosec.exchange/@infosecdj/117213266219165204 Dmitry is working through the dies I sent him, more to follow soon

yeah more of that is coming -- let me know if you want them posted here :)

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InfoSecDJ

yeah more of that is coming -- let me know if you want them posted here :)

Feel free to post the ones you've already imaged, if you like

Once you've finished the whole batch, we can make an announcement for all to see.

@Leo Moser (mole99) http://infosecdj.net:8086/map/#wafer-space

12:08 p.m.

No TT ones

tnt

No TT ones

Yes, it seems that the package prepared by Tim didn't include any of the TTP2/TTPG dies. If you still have any left over, maybe you could get those to Dmitry?

Leo Moser (mole99)

Yes, it seems that the package prepared by Tim didn't include any of the TTP2/TTPG dies. If you still have any left over, maybe you could get those to Dmitry?

I have some from Tim which I did not get to yet, maybe these are the ones?

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I guess we'll find out

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some more eye candy for you folks

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2:35 p.m.

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-mosb/infosecdj_mz_nikpa40x

2:36 p.m.

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-ishi/infosecdj_mz_nikpa40x

2:36 p.m.

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-as03/infosecdj_mz_nikpa40x

InfoSecDJ

I have some from Tim which I did not get to yet, maybe these are the ones?

Honestly, I'd expect a spare raw ttgf0p2 die for such imaging to be easily furnished and it's not like that'd be hard to send to you.

namibj

Honestly, I'd expect a spare raw ttgf0p2 die for such imaging to be easily furnished and it's not like that'd be hard to send to you.

Good to know. Let's get back to it after I am through all the samples on hand.

Thinking of designing the PCBs to bring-up my run 2 chips already

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Do we know yet what the COB PCB layout will be for run 2?

https://github.com/jonahsaunders/inductor-studio/tree/main

GitHub - jonahsaunders/inductor-studio

Contribute to jonahsaunders/inductor-studio development by creating an account on GitHub.

9:56 p.m.

I made this with the new GPT-6 Astra in 20 minutes Haven't tested it thoroughly, but just did it as a test

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Tholin

Do we know yet what the COB PCB layout will be for run 2?

I’m gonna assume the default COB PCB is the same as last time. I did not customize the padring this time.

Tholin

I’m gonna assume the default COB PCB is the same as last time. I did not customize the padring this time.

I’m fairly certain pinout won’t change for 1x1. Finer details like number of layers and position of vias might. Pinout for 1x0p5 might change slightly as the ordering of 4 pins is reversed compared to the die which is likely a recipe for confusion in future I don’t think 0p5x1 would change, but the run 1 ones aren’t tested yet. For quarter slot there was talk of using a different connector (fewer pins = cheaper)

Leo Moser (mole99)

Yes, it seems that the package prepared by Tim didn't include any of the TTP2/TTPG dies. If you still have any left over, maybe you could get those to Dmitry?

I have no idea what the package was that I gave you

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InfoSecDJ

some more eye candy for you folks

These are super cool!

InfoSecDJ

some more eye candy for you folks

I would love to host a copy on https://data.wafer.space

9:22 a.m.

@InfoSecDJ - Could you do an entire wafer?

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Tim 'mithro' Ansell

@InfoSecDJ - Could you do an entire wafer?

Most probably not :D That said, it'd be interesting to have a look at test tiles and features in scribe lanes that got cut (edited)

Tim 'mithro' Ansell

I would love to host a copy on https://data.wafer.space

I'll give you all the links when I am done with the whole run, feel free to host a copy there

InfoSecDJ

Most probably not :D That said, it'd be interesting to have a look at test tiles and features in scribe lanes that got cut (edited)

I'd assume a mere full reticle would be most of the interesting content? Unless someone considers the edge partials particularly interesting.

InfoSecDJ

Most probably not :D That said, it'd be interesting to have a look at test tiles and features in scribe lanes that got cut (edited)

How about the original masks?

Tim 'mithro' Ansell

How about the original masks?

I could give it a try, though the resolution/magnification will be very low due to the area that needs to be covered. One 1x1 die takes about ~16h to image

Masks are 4x larger ? So 10x magnification of mask is the same as 40x of the die.

9:54 a.m.

But yeah still ... full mask is ~ 40x the area of a chip and then there is like ... 25 of them or so ? That's 1.8 year worth

The tyranny of numbers :D

@InfoSecDJ - I think we worked out that my automated microscope (a Labsmore thing from @digshadow) at PS1 would take roughly like 17 hours to do a mask, which is like one a day.

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9:56 a.m.

@carlfk and @Andrew Wingate started doing some stuff which got uploaded at https://data.wafer.space/jaguar-ps1/pyuscope/data/scan/

Tim 'mithro' Ansell

@InfoSecDJ - I think we worked out that my automated microscope (a Labsmore thing from @digshadow) at PS1 would take roughly like 17 hours to do a mask, which is like one a day.

All depends on the quality+resolution you want to get :)

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InfoSecDJ

All depends on the quality+resolution you want to get :)

Always more!

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namibj started a thread. 2026-09-07 2:54 p.m.

Hmmmm at 100nm pixel size if running 20 fps (as a Pi5 could, at least with an LED strobe) and 50% overlap in both directions (so each spot gets nominally 4 captures coverage) it's "just" 34 seconds plus no-capture times caused by whatever acceleration limits the motion stage imposes at the ends of the zig-zag scan.

I wonder if we should set up something like https://www.honeypotbot.com/ that esden (1bitsquared) just setup on his discord? (edited)

Home | Honeypot

The official guide to Honeypot, the antispam bot for discord!

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I setup something like that on mine and it's helped a bunch to cut down on spam

7:49 p.m.

not perfect, but catches a lot

http://infosecdj.net/map/wafer-space/gf180mcu-ws1-ocd1/infosecdj_mz_nikpa40x

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cc @Tim Edwards

good news, I am through all the samples @Leo Moser (mole99) sent me. browsable images here: http://infosecdj.net/map/#wafer-space if you need single images and/or previews, ping me for download urls.

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These seem pretty cool - https://makerworld.com/en/models/2819094-field-effect-transistor-models-fet-v2#profileId-3139175